19 research outputs found

    An asynchronous ternary logic signaling system

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    Sparse Distributed Memory Using Rank-Order Neural Codes

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    Building a Spiking Neural Network Model of the Basal Ganglia on SpiNNaker

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    We present a biologically-inspired and scalable model of the Basal Ganglia (BG) simulated on the SpiNNaker machine, a biologically-inspired low-power hardware platform allowing parallel, asynchronous computing. Our BG model consists of six cell populations, where the neuro-computational unit is a conductance-based Izhikevich spiking neuron; the number of neurons in each population is proportional to that reported in anatomical literature. This model is treated as a single-channel of action-selection in the BG, and is scaled-up to three channels with lateral cross-channel connections. When tested with two competing inputs, this three-channel model demonstrates action-selection behaviour. The SpiNNaker-based model is mapped exactly on to SpineML running on a conventional computer; both model responses show functional and qualitative similarity, thus validating the usability of SpiNNaker for simulating biologically-plausible networks. Furthermore, the SpiNNaker-based model simulates in real time for time-steps 1 ms; power dissipated during model execution is & #x2248;1.8 W

    Bounded Model Checking for Parametric Timed Automata

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    Abstract. The paper shows how bounded model checking can be ap-plied to parameter synthesis for parametric timed automata with con-tinuous time. While it is known that the general problem is undecidable even for reachability, we show how to synthesize a part of the set of all the parameter valuations under which the given property holds in a model. The results form a complete theory which can be easily applied to parametric verification of a wide range of temporal formulae – we present such an implementation for the existential part of CTL −X. 1 Introduction and related work The growing abundance of complex systems in real world, and their presence in critical areas fuels the research in formal specification and analysis. One of the established methods in systems verification is model checking, where the system is abstracted into the algebraic model (e.g. various versions of Kripke structures

    Breaking Step - The Return Of Asynchronous Logic

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    this paper I will attempt to explain why. Why not just use a clock

    On-chip timing reference for self-timed microprocessor

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    On-chip and inter-chip networks for modelling large-scale neural systems

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    Abstract—The real-time modeling of large systems of spiking neurons is computationally very demanding in terms of processing power, synaptic weight memory requirements and communication throughput. We propose to build a high-performance computer for this purpose with a multicast communications infrastructure inspired by neurobiology. The core component will be a chip multiprocessor incorporating some tens of small embedded processors, interconnected by an NoC that carries spike events between processors on the same or different chips. The design emphasizes modeling flexibility, power-efficiency, and fault-tolerance, and is intended to yield a general-purpose platform for the real-time simulation of large-scale spiking neural systems. I
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